Experiments were carried out to investigate the effect of reversing the heat flux direction during cooling on the formation of voids during the reflow process. Under different upward and downward solidification conditions, 480 high-lead (90Pb8Sn2Ag) solder joints of flip-chip assemblies were processed. The solder samples were then microsectioned to determine the size and location of voids. The results show that reversing the flow direction during cooling has a significant effect on the final void formation. For the case of the melting direction from top (flip-chip side) to bottom (test board side), reversing the heat flux direction results in solidification direction from top to bottom. The percentage of defective bumps was found to be 28% and the volume of voids per defective bump was 1.5%. This is the best reflow methodology to minimize voids. Without reversing the heat flux the defective bumps were 80% with 4.0% void volume. In the case of solidification direction/melting direction from bottom to top, the percentage of defective bumps increases from 40% to 51%, accompanying a rise of the volume of voids from 3.0% to 3.7%.

1.
Lau
,
J. H.
, and
Pao
,
Y.-H.
, 1997,
Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies
, McGraw-Hill, New York, Chap. 6.
2.
Chiu
,
C. S.
, and
Lee
,
N. C.
, 1997, “
Voiding in BGA at Solder Bumping Stage
,”
International Symposium on Microelectronics
, pp.
462
471
.
3.
Chan
,
Y. C.
,
Xie
,
D. J.
, and
Lai
,
J. K. L.
, 1995, “
Characteristics of Porosity in Solder Pastes During Infrared Reflow Soldering
,”
J. Mater. Sci.
0022-2461,
30
(
21
), pp.
5543
5550
.
4.
Goenka
,
L.
, and
Achari
,
A.
, 1995, “
Void Formation in Flip-Chip Solder Bumps—Part I
,”
Proceedings of the 18th IEEE/CPMT Symposium, Austin, TX
, pp.
14
19
.
5.
Bailey
,
C.
,
Lu
,
H.
and
Wheeler
,
D.
, 2002, “
Computational Modeling Techniques for Reliability of Electronic Components on Printed Circuit Boards
,”
Appl. Numer. Math.
0168-9274,
40
, pp.
101
117
.
6.
Goenka
,
L.
, and
Achari
,
A.
, 1996, “
Void Formation in Flip Chip Solder Bumps—Part II
,”
Proceedings of the 19th IEEE/CPMT Symposium, Austin, TX
, pp.
430
437
.
7.
Panton
,
R. L.
,
Lee
,
J. W.
,
Goenka
,
L.
, and
Achari
,
A.
, 2003, “
Simulation of Void Growth in Molten Solder Bumps
,”
ASME J. Electron. Packag.
1043-7398,
125
(
3
), pp.
329
334
.
8.
Wang
,
D.
, and
Panton
,
R. L.
, 2005, “
Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies
,”
ASME J. Electron. Packag.
1043-7398,
127
(
2
), pp.
120
126
.
You do not currently have access to this content.