In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.
Issue Section:
Research Papers
Keywords:
3D packaging
References
1.
Beyne
, E.
,2011
, “Through-Silicon Via Technology for 3D IC
,” Ultra-Thin Chip Technology and Applications
, Springer
, Berlin
, pp. 93
–108
.2.
Lau
, J. H.
, 2014
, “Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration
,” ASME. J. Electron. Packag.
, 136
(4
), p. 040801
.3.
Agonafer
, D.
, Kaisare
, A.
, Hossain
, M.
, Lee
, Y.
, Dewan-Sandur
, B.
, Dishongh
, T.
, and Pekin
, S.
, 2008
, “Thermo-Mechanical Challenges in Stacked Packaging
,” Heat Transfer Eng.
, 29
(2
), pp. 134
–148
.4.
Venkatadri
, V.
, Sammakia
, B.
, Srihari
, K.
, and Santos
, D.
, 2011
, “A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems
,” ASME. J. Electron. Packag.
, 133
(4
), p. 041011
.5.
Kandlikar
, S. G.
, 2014
, “Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits
,” ASME. J. Electron. Packag.
, 136
(2
), p. 024001
.6.
Matsumoto
, K.
, Ibaraki
, S.
, Sueoka
, K.
, Sakuma
, K.
, Kikuchi
, H.
, Orii
, Y.
, Yamada
, F.
, Fujihara
, K.
, Takamatsu
, J.
, and Kondo
, K.
, 2013
, “Thermal Design Guidelines for a Three-Dimensional (3D) Chip Stack, Including Cooling Solutions
,” 29th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM
), San Jose, CA, Mar. 17–21.7.
Sikka
, K.
, Wakil
, J.
, Toy
, H.
, and Hsichang
Liu
, 2012
, “An Efficient Lid Design for Cooling Stacked Flip-Chip 3D Packages
,” IEEE 13th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
(ITherm
), San Diego, CA, May 30–June 1, pp. 606
–611
.8.
Santos
, C.
, Vivet
, P.
, Dutoit
, D.
, Garrault
, P.
, Peltier
, N.
, and Reis
, R.
, 2013
, “System-Level Thermal Modeling for 3D Circuits: Characterization With a 65nm Memory-on-Logic Circuit
,” IEEE International 3D Systems Integration Conference
(3DIC
), San Francisco, CA, Oct. 2–4.9.
Oprins
, H.
, Cherman
, V. O.
, Vandevelde
, B.
, Van der Plas
, G.
, Marchal
, P.
, and Beyne
, E.
, 2012
, “Numerical and Experimental Characterization of the Thermal Behavior of a Packaged DRAM-on-Logic Stack
,” IEEE 62nd Electronic Components and Technology Conference
(ECTC
), San Diego, CA, May 29–June 1, pp. 1081
–1088
.10.
Lall
, B. S.
, Guenin
, B. N.
, and Molnar
, R. J.
, 1995
, “Methodology for Thermal Evaluation of Multichip Modules
,” IEEE Trans. Comp., Pack., Manu. Tech., Part A
, 18
(4
), pp. 758
–764
.11.
Beyne
, E.
, 2015
, “Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration
,” IEEE Trans. Comp., Pack., Manu. Tech.
(in press).12.
De Vos
, J.
, Jourdain
, A.
, Erismis
, M. A.
, Zhang.
, W.
, De Munck
, K.
, La Manna
, A.
, Tezcan
, D. S.
, and Soussan
, P.
, 2011
, “High Density 20 μm Pitch CuSn Microbump Process for High-End 3D Applications
,” IEEE 61st IEEE Electronic Components and Technology Conference
(ECTC
), Lake Buena Vista, FL, May 31–June 3, pp. 27
–31
.13.
De Vos
, J.
, Cherman
, V.
, Detalle
, M.
, Wang
, T.
, Salahouelhadj
, A.
, Daily
, R.
, Van der Plas
, G.
, and Beyne
, E.
, 2014
, “Comparative Study of 3D Stacked IC and 3D Interposer Integration: Processing and Assembly Challenges
,” IEEE International 3D Systems Integration Conference
(3DIC
), Kinsale, Ireland, Dec. 1
–3.14.
Mital
, M.
, Pang
, Y.
, and Scott
, E. P.
, 2008
, “Evaluation of Thermal Resistance Matrix Method for an Embedded Power Electronic Module
,” IEEE Trans. Comp., Pack., Manu. Tech.
, 31
(2
) pp. 382
–387
.15.
JEDEC
, 2007
, “Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air)
,” JEDEC Solid State Technology Association, Arlington, VA, JEDEC
Standard No. 51–2A. 16.
Jain
, A.
, Jones
, R. E.
, Chatterjee
, R.
, and Pozder
, S.
, 2010
, “Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits
,” IEEE Trans. Comp., Pack., Manu. Tech.
, 33
(1
), pp. 56
–63
.17.
Choobineh
, L.
, and Jain
, A.
, 2015
, “An Explicit Analytical Model for Rapid Computation of Temperature Field in a Three-Dimensional Integrated Circuit (3D IC)
,” Int. J. Therm. Sci.
, 87
, pp. 103
–109
.18.
Chauhan
, A.
, Sammakia
, B.
, Afram
, F.F.
, Ghose
, K.
, Refai-Ahmed
, G.
, and Agonafer
, D.
, 2013
, “Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias
,” ASME. J. Electron. Packag.
, 135
(4
), p. 041006
.19.
Maggioni
, F. L. T.
, Oprins
, H.
, Beyne
, E.
, De Wolf
, I.
, and Baelmans
, M.
, 2014
, “Fast Convolution Based Thermal Model for 3D-ICs: Methodology, Accuracy Analysis and Package Impact
,” Microelectron. J.
, 45
(12
), pp. 1746
–1752
.20.
Sridhar
, A.
, Vincenzi
, A.
, Atienza
, D.
, and Brunschwiler
, T.
, 2014
, “3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs
,” IEEE Trans. Comp.
, 63
(10
), pp. 2576
–2589
.21.
Matsumoto
, K.
, Ibaraki
, S.
, Sueoka
, K.
, Sakuma
, K.
, Kikuchi
, H.
, Orii
, Y.
, and Yamada
, F.
, 2012
, “Experimental Thermal Resistance Evaluation of a Three-Dimensional (3D) Chip Stack, Including the Transient Measurements
,” IEEE 28th Semiconductor Thermal Measurement and Management Symposium
(SEMITHERM
), San Jose, CA, Mar. 18–22, pp. 8
–13
.22.
Colgan
, E. G.
, Andry
, P.
, Dang
, B.
, Magerlein
, J. H.
, Maria
, J.
, Polastre
, R. J.
, and Wakil
, J.
, 2012
, “Measurement of Microbump Thermal Resistance in 3D Chip Stacks
,” IEEE 28th Semiconductor Thermal Measurement and Management Symposium
(SEMI-THERM
), San Jose, CA, Mar. 18–22, pp. 1
–7
.23.
Gonzalez
, M.
, Vandevelde
, B.
, Ivankovic
, A.
, Cherman
, V.
, Debecker
, B.
, Lofrano
, M.
, De Wolf
, I.
, Beyer
, G.
, Swinnen
, B.
, Tokei
, Z.
, and Beyne
, E.
, 2012
, “Chip Package Interaction (CPI): Thermo Mechanical Challenges in 3D Technologies
,” IEEE 14th Electronics Packaging Technology Conference
(EPTC
), Singapore, Dec. 5–7, pp. 547
–551
.24.
Frear
, D. R.
, Burchett
, S. N.
, Morgan
, H. S.
, and Lau
, J. H.
, 1994
, Mechanics of Solder Alloy Interconnects
, Kluwer
, Amsterdam
.25.
Peng
, L.
, Kim
, S.-W.
, Soules
, M.
, Markus
, G.
, Zoberbier
, M.
, Sleeckx
, E.
, Struyf
, H.
, Miller
, A.
, and Beyne
, E.
, 2014
, “W2W Permanent Stacking for 3D System Integration
,” IEEE 16th Electronics Packaging Technology Conference
(EPTC
), Singapore, Dec. 3–5.26.
Brunschwiler
, T.
, Schindler-Saefkow
, F.
, Gordin
, R.
, Haupt
, M.
, and Schlottig
, G.
, 2014
, “Study of the Compound of Properties of Percolating and Neck-Based Thermal Underfills
,” IEEE 14th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
(ITherm
), Orlando, FL, May 27–30, pp. 227
–234
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