Modeling Thermal Microspreading Resistance in Via Arrays

As thermal management techniques for three-dimensional (3D) chip stacks and other high-power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased. To reduce the computational costs and time in the thermal analysis of through-layer via (TXV) structures, much research to date has focused on defining effective anisotropic thermal properties for a pseudohomogeneous medium using isothermal boundary conditions. While such an approach eliminates the need to model heat flow through individual vias, the resulting properties are found to depend on the specific boundary conditions applied to a unit TXV cell. More specifically, effective properties based on isothermal boundary conditions fail to capture the local “microspreading” resistance associated with more realistic heat flux distributions and local hot spots on the surface of these substrates. This work assesses how the thermal microspreading resistance present in arrays of vias in interposers, substrates, and other package components can be properly incorporated into the modeling of these arrays. We present the conditions under which spreading resistance plays a major role in determining the thermal characteristics of a via array and propose methods by which designers can both account for the effects of microspreading resistance and mitigate its contribution to the overall thermal behavior of such substrate–via systems. Finite element modeling (FEM) of TXV unit cells is performed using commercial simulation software (ansys).