Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.
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June 2017
Research-Article
Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction
Valeriy Sukharev,
Valeriy Sukharev
Mem. ASME
Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538
e-mail: valeriy_sukharev@mentor.com
Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538
e-mail: valeriy_sukharev@mentor.com
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Henrik Hovsepyan,
Henrik Hovsepyan
Mentor Graphics Corporation,
16 Halabyan Street,
Yerevan 0038, Armenia
e-mail: henrik_hovsepyan@mentor.com
16 Halabyan Street,
Yerevan 0038, Armenia
e-mail: henrik_hovsepyan@mentor.com
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Mark Nakamoto,
Mark Nakamoto
Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: nakamoto@qti.qualcomm.com
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: nakamoto@qti.qualcomm.com
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Wei Zhao,
Wei Zhao
Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: weizhao@qti.qualcomm.com
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: weizhao@qti.qualcomm.com
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Uwe Muehle,
Uwe Muehle
Department of Microelectronic
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: uwe.muehle@ikts-extern.fraunhofer.de
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: uwe.muehle@ikts-extern.fraunhofer.de
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Ehrenfried Zschech
Ehrenfried Zschech
Department of Microelectronic
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: ehrenfried.zschech@ikts.fraunhofer.de
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: ehrenfried.zschech@ikts.fraunhofer.de
Search for other works by this author on:
Valeriy Sukharev
Mem. ASME
Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538
e-mail: valeriy_sukharev@mentor.com
Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538
e-mail: valeriy_sukharev@mentor.com
Jun-Ho Choy
Armen Kteyan
Henrik Hovsepyan
Mentor Graphics Corporation,
16 Halabyan Street,
Yerevan 0038, Armenia
e-mail: henrik_hovsepyan@mentor.com
16 Halabyan Street,
Yerevan 0038, Armenia
e-mail: henrik_hovsepyan@mentor.com
Mark Nakamoto
Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: nakamoto@qti.qualcomm.com
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: nakamoto@qti.qualcomm.com
Wei Zhao
Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: weizhao@qti.qualcomm.com
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: weizhao@qti.qualcomm.com
Riko Radojcic
Uwe Muehle
Department of Microelectronic
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: uwe.muehle@ikts-extern.fraunhofer.de
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: uwe.muehle@ikts-extern.fraunhofer.de
Ehrenfried Zschech
Department of Microelectronic
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: ehrenfried.zschech@ikts.fraunhofer.de
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: ehrenfried.zschech@ikts.fraunhofer.de
1Corresponding author.
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 14, 2016; final manuscript received March 30, 2017; published online June 12, 2017. Assoc. Editor: S. Ravi Annapragada.
J. Electron. Packag. Jun 2017, 139(2): 020906 (12 pages)
Published Online: June 12, 2017
Article history
Received:
December 14, 2016
Revised:
March 30, 2017
Citation
Sukharev, V., Choy, J., Kteyan, A., Hovsepyan, H., Nakamoto, M., Zhao, W., Radojcic, R., Muehle, U., and Zschech, E. (June 12, 2017). "Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction." ASME. J. Electron. Packag. June 2017; 139(2): 020906. https://doi.org/10.1115/1.4036402
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