Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.
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June 2017
Research-Article
Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits
Leila Choobineh,
Leila Choobineh
Mem. ASME
Mechanical Engineering,
SUNY Polytechnic Institute,
100 Seymour Road,
Utica, NY 13502
e-mail: Leila.choobineh@sunyit.edu
Mechanical Engineering,
SUNY Polytechnic Institute,
100 Seymour Road,
Utica, NY 13502
e-mail: Leila.choobineh@sunyit.edu
Search for other works by this author on:
Jared Jones,
Jared Jones
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
Search for other works by this author on:
Ankur Jain
Ankur Jain
Mem. ASME
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
e-mail: jaina@uta.edu
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
e-mail: jaina@uta.edu
Search for other works by this author on:
Leila Choobineh
Mem. ASME
Mechanical Engineering,
SUNY Polytechnic Institute,
100 Seymour Road,
Utica, NY 13502
e-mail: Leila.choobineh@sunyit.edu
Mechanical Engineering,
SUNY Polytechnic Institute,
100 Seymour Road,
Utica, NY 13502
e-mail: Leila.choobineh@sunyit.edu
Jared Jones
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
Ankur Jain
Mem. ASME
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
e-mail: jaina@uta.edu
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
e-mail: jaina@uta.edu
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 16, 2016; final manuscript received March 27, 2017; published online June 12, 2017. Assoc. Editor: Justin A. Weibel.
J. Electron. Packag. Jun 2017, 139(2): 020908 (6 pages)
Published Online: June 12, 2017
Article history
Received:
December 16, 2016
Revised:
March 27, 2017
Citation
Choobineh, L., Jones, J., and Jain, A. (June 12, 2017). "Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits." ASME. J. Electron. Packag. June 2017; 139(2): 020908. https://doi.org/10.1115/1.4036404
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