Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.
Issue Section:
Review Article
References
1.
Tan
, C. S.
, Gutmann
, R. J.
, and Reif
, L. R.
, 2009
, Wafer Level 3-D ICs Process Technology
, Springer Science & Business Media
, New York, p. 3
.2.
Akasaka
, Y.
, 1986
, “Three-Dimensional IC Trends
,” Proc. IEEE
, 74
(12), pp. 1703
–1714
.3.
Chen
, K. N.
, Chang
, S. M.
, Fan
, A.
, Tan
, C. S.
, Shen
, S. C.
, and Reif
, R.
, 2005
, “Process Development and Bonding Quality Investigations of Silicon Layer Stacking Based on Copper Wafer Bonding
,” Appl. Phys. Lett.
, 87
(3), p. 031909
.4.
Jang
, E. J.
, Pfeiffer
, S.
, Kim
, B.
, Matthias
, T.
, Hyun
, S.
, Lee
, H. J.
, and Park
, Y. B.
, 2008
, “Effect of Post-Annealing Conditions on Interfacial Adhesion Energy of Cu-Cu Bonding for 3-D IC Integration
,” Korean J. Mater. Res.
, 18
(4), pp. 204
–210
.5.
Chen
, K. N.
, Tan
, C. S.
, Fan
, A.
, and Reif
, R.
, 2005
, “Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration During Current Stressing
,” Appl. Phys. Lett.
, 86
(1), p. 011903
.6.
Ruythooren
, W.
, Beltran
, A.
, and Labie
, R.
, 2007
, “Morphology and Bond Strength of Copper Wafer Bonding
,” Ninth Electronics Packaging Technology Conference
, Singapore, Dec. 10–12.7.
Chen
, K. N.
, Fan
, A.
, and Reif
, R.
, 2004
, “Morphology and Bond Strength of Copper Wafer Bonding
,” Electrochem. Solid St. Lett.
, 7
(1), pp. G14
–G16
.8.
Tan
, C. S.
, Gutmann
, R. J.
, and Reif
, L. R.
, 2008
, Overview of Wafer Level 3D ICs, in Wafer Level 3-D ICs Process Technology
, Springer
, New York
, pp. 1
–11
.9.
Peng
, L.
, Li
, H.
, Lim
, D. F.
, Gao
, S.
, and Tan
, C. S.
, 2008
, “High-Density 3-D Interconnect of Cu–Cu Contacts With Enhanced Contact Resistance by Self-Assembled Monolayer (SAM) Passivation
,” IEEE Trans. Electron. Devices
, 58
(8
), pp. 2500
–2506
.10.
Lee
, K. W.
, Nakamura
, T.
, Sakuma
, K.
, Park
, K. T.
, Shimazutsu
, H.
, Miyakawa
, N.
, Kim
, K. Y.
, Kurino
, H.
, and Koyanagi
, M.
, 2000
, “Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip
,” Jpn. J. Appl. Phys.
, 39
(4S
), pp. 2473
–2477
.11.
Fan
, A.
, Chen
, K. N.
, and Reif
, R.
, 2001, “Three-Dimensional Integration With Copper Wafer Bonding
,” Electrochemical Society Spring Meeting 2001–2002: ULSI Process Integration Symposium
, Washington, DC, Mar. 24–31, pp. 124
–128
.12.
Hu
, Y. C.
, and Chen
, K. N.
, 2016
, “A Novel Bonding Approach and Its Electrical Performance for Flexible Substrate Integration
,” IEEE J. Electron. Devices Soc.
, 4
(4
), pp. 185
–188
.13.
Save
, D.
, Braud
, F.
, Torres
, J.
, Binder
, F.
, Muller
, C.
, Weidner
, J. O.
, and Hasse
, W.
, 1997
, “Electromigration Resistance of Copper Interconnects
,” Microelectron. Eng.
, 33
(1–4), pp. 75
–84
.14.
Huffman
, A.
, Lannon
, J.
, Lucck
, M.
, Gregory
, C.
, and Temple
, D.
, 2009
, “Fabrication and Characterization of Metal-to-Metal Interconnect Structures for 3-D Integration
,” Materials and Technologies for 3-D Integration Symposium
, Warrendale, PA, Dec. 1–3, pp. 107
–119
.15.
Tan
, C. S.
, and Reif
, R.
, 2005
, “Silicon Multilayer Stacking Based on Copper Wafer Bonding
,” Electrochem. Solid-State Lett.
, 8
(6), pp. G147
–G149
.16.
Peng
, L.
, Li
, H.
, Lim
, D.
, Lo
, G.
, Kwong
, D.
, and Tan
, C.
, 2011
, “High Density Bump-Less Cu–Cu Bonding With Enhanced Quality Achieved by Pre-Bonding Temporary Passivation for 3D Wafer Stacking
,” IEEE International Symposium on VLSI Technology, Systems and Applications
(VLSI-TSA
), Hsinchu, Taiwan, Apr. 25–27, pp. 1
–2
.17.
Li, Y. A., Bower, R. W., and Bencuya, I., 1998, “
Low Temperature Copper to Copper Direct Bonding
,” Jpn. J. Appl. Phys.
, 37
(9A), pp. L1068–L1069.18.
Made, R. I., Lan, P., Li, H. Y., Gan, C. L., and Tan, C. S.,
2011
, “Study of the Evolution of Cu-Cu Bonding Interface Imperfection Under Direct Current Stressing for Three Dimensional Integrated Circuits
,” IEEE International Interconnect Technology Conference and Materials for Advanced Metallization
(IITC/MAM
), Dresden, Germany, May 8–12.19.
Moriceau
, H.
, Rieutord
, F.
, Fournel
, F.
, Di Cioccio
, L.
, Moulet
, C.
, Libralesso
, L.
, Gueguen
, P.
, Taibi
, R.
, and Deguet
, C.
, 2012
, “Low Temperature Direct Bonding: An Attractive Technique for Hetero Structures Build-Up
,” Microelectron. Reliab.
, 52
(2), pp. 331
–341
.20.
Takagi
, H.
, Kikuchi
, K.
, Maeda
, R.
, Chung
, T.
, and Suga
, T.
, 1996
, “Surface Activated Bonding of Silicon Wafers at Room Temperature
,” Appl. Phys. Lett.
, 68
(16), pp. 2222
–2224
.21.
Shigetou
, A.
, Itoh
, T.
, and Suga
, T.
, 2006
, “Bumpless Interconnect of Cu Electrodes in Millions-Pins Level
,” IEEE 56th Electronic Components and Technology Conference
(ECTC
), San Diego, CA, May 30–June 2, pp.1223–1226.22.
Tsukamoto
, K.
, Higurashi
, E.
, and Suga
, T.
, 2010
, “Evaluation of Surface Microroughness for Surface Activated Bonding
,” IEEE
CPMT Symposium
Japan, Tokyo, Japan, Aug. 24–26, pp. 1–4.23.
Wakamatsu
, T.
, Suga
, T.
, Akaike
, M.
, Shigetou
, A.
, and Higurashi
, E.
, 2007
, “Effect of SAB Process on GaN Surfaces for Low Temperature Bonding
,” IEEE 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics
(Polytronic
), Tokyo, Japan, Jan. 15–18, pp. 41
–44
.24.
Wang
, C.
, and Suga
, T.
, 2010
, “A Novel Room-Temperature Wafer Direct Bonding Method by Fluorine Containing Plasma Activation
,” IEEE 60th Electronic Components and Technology Conference
(ECTC
), Las Vegas, NV, June 1–4, pp. 303
–308
.25.
Shigetou
, A.
, Itoh
, T.
, Sawada
, K.
, and Suga
, T.
, 2008
, “Bumpless Interconnect of 6-μm-Pitch Cu Electrodes at Room Temperature
,” IEEE Trans. Adv. Packag.
, 31
(3), pp. 473
–478
.26.
Fan
, J.
, Lim
, D. F.
, and Tan
, C. S.
, 2013
, “Effects of Surface Treatment on the Bonding Quality of Wafer-Level Cu-to-Cu Thermo-Compression Bonding for 3D Integration
,” J. Micromech. Microeng.
, 23
, p. 045025
.27.
Jang
, E.-J.
, Hyun
, S.
, Lee
, H.-J.
, and Park
, Y.-B.
, 2009
, “Effect of Wet Pretreatment on Interfacial Adhesion Energy of Cu–Cu Thermocompression Bond for 3D IC Packages
,” J. Electron. Mater.
, 38
, pp. 2449
–2454
.28.
Swinnen
, B.
, Ruythooren
, W.
, Moor
, P. D.
, Bogaerts
, L.
, Carbonell
, L.
, Munck
, K. D.
, Eyckens
, B.
, Stoukatch
, S.
, Sabuncuoglu Tezcan
, D.
, Tokei
, Z.
, Vaes
, J.
, Van Aelst
, J.
, and Beyne
, E.
, 2006
, “3D Integration by Cu–Cu Thermo-Compression Bonding of Extremely Thinned Bulk-Si Die Containing 10 μm Pitch Through-Si Vias
,” International Electron Devices Meeting
(IEDM
), San Francisco, CA, Dec. 11–13, pp. 1
–4
.29.
Huffman
, A.
, Lannon
, J.
, Lueck
, M.
, Gregory
, C.
, and Temple
, D.
, 2009
, “Fabrication and Characterization of Metal-to-Metal Interconnect Structures for 3-D Integration
,” J. Instrum.
, 4
(3), p. P03006
.30.
Chen
, K.
, Tan
, C.
, Fan
, A.
, and Reif
, R.
, 2005
, “Copper Bonded Layers Analysis and Effects of Copper Surface Conditions on Bonding Quality for Three Dimensional Integration
,” J. Electron. Mater.
, 34
(12), pp. 1464
–1467
.31.
Chen
, K.
, Fan
, A.
, Tan
, C.
, and Reif
, R.
, 2006
, “Bonding Parameters of Blanket Copper Wafer Bonding
,” J. Electron. Mater.
, 35
(2), pp. 230
–234
.32.
Peng
, L.
, Li
, H. Y.
, Lim
, D. F.
, Made
, R. I.
, Lo
, G.-Q.
, Kwong
, D.-L.
, and Tan
, C. S.
, 2010
, “Fine-Pitch Bump-Less Cu–Cu Bonding for Wafer-on-Wafer Stacking and Its Quality Enhancement
,” IEEE International 3D Systems Integration Conference
(3DIC
), Munich, Germany, Nov. 16–18, pp. 1
–5
.33.
Saeidi
, N.
, Rogers
, T.
, Draisey
, A.
, Davies
, R.
, Casey
, D.
, Colinge
, C.
, Demosthenous
, A.
, and Donaldson
, N.
, 2012, “The Effects of In-Situ Formic Acid Treatment on Oxide Reduction for Copper Wafer Bonding,” AML Micro Engineering Ltd., Kowloon, Hong Kong.34.
Wei
, J.
, Nai
, S. M. L.
, Ang
, X. F.
, and Yung
, K. P.
, 2009
, “Advanced High Density Interconnect Materials and Techniques
,” International Conference on Electronic Packaging Technology and High Density Packaging
(ICEPT-HDP
), Beijing, China, Aug. 10–13, pp. 6
–13
.35.
Ang
, X.
, Lin
, A.
, Wei
, J.
, Chen
, Z.
, and Wong
, C.
, 2008
, “Low Temperature Copper–Copper Thermocompression Bonding
,” Tenth IEEE Electronics Packaging Technology Conference
(EPTC
), Singapore, Dec. 9–12, pp. 399
–404
.36.
Tan
, C. S.
, Lim
, D. F.
, Ang
, X. F.
, Wei
, J.
, and Leong
, K. C.
, 2012
, “Low Temperature Cu–Cu Thermo-Compression Bonding With Temporary Passivation of Self-Assembled Monolayer and Its Bond Strength Enhancement
,” Microelectron. Reliab.
, 52
(2
), pp. 321
–324
.37.
Tan
, C. S.
, Lim
, D. F.
, Singh
, S. G.
, Goulet
, S. K.
, and Bergkvist
, M.
, 2009
, “Cu–Cu Diffusion Bonding Enhancement at Low Temperature by Surface Passivation Using Self-Assembled Monolayer of Alkane-Thiol
,” Appl. Phys. Lett.
, 95
(19
), p. 192108
.38.
Tan
, C. S.
, and Lim
, D. F.
, 2013
, “Cu Surface Passivation With Self-Assembled Monolayer (SAM) and Its Application for Wafer Bonding at Moderately Low Temperature
,” ECS Trans.
, 50
(7
), pp. 115
–123
.39.
Ghosh
, T.
, Krushnamurthy
, K.
, Panigrahi
, A. K.
, Dutta
, A.
, Subrahmanyam
, C.
, Vanjari
, S. R. K.
, and Singh
, S. G.
, 2015
, “Facile Non Thermal Plasma Based Desorption of Self Assembled Monolayers for Achieving Low Temperature and Low Pressure Cu–Cu Thermo-Compression Bonding
,” RSC Adv.
, 5
(125
), pp. 103643
–103648
.40.
Chen
, H. Y.
, Hsu
, S. Y.
, and Chen
, K. N.
, 2013
, “Electrical Performance and Reliability Investigation of Co-Sputtered Cu/Ti Bonded Interconnects
,” IEEE Trans. Electron. Devices
, 60
(10
), pp. 3521
–3526
.41.
Chen
, H. Y.
, Hsu
, S. Y.
, and Chen
, K. N.
, 2013
, “Co-Sputtered Cu/Ti Bonded Interconnects for 3D Integration Applications
,” IEEE International Symposium on VLSI Technology, Systems, Applications
(VLSI-TSA
), Hsinchu, Taiwan, Apr. 22–24, pp. 1
–2
.42.
Huang
, Y. P.
, Chien
, Y. S.
, Tzeng
, R. N.
, Shy
, M. S.
, Lin
, T. H.
, Chen
, K. H.
, Chiu
, C. T.
, Chiou
, J. C.
, Chuang
, C. T.
, Hwang
, W.
, Tong
, H. M.
, and Chen
, K. N.
, 2013
, “Novel Cu-to-Cu Bonding With Ti Passivation at 180 °C in 3-D Integration
,” IEEE Electron. Dev. Lett.
, 34
(12
), pp. 1551
–1553
.43.
Huang
, Y. P.
, Chien
, Y. S.
, Tzeng
, R. N.
, Shy
, M. S.
, Lin
, T. H.
, Chen
, K. H.
, Chuang
, C. T.
, Hwang
, W.
, Chiu
, C. T.
, Tong
, H. M.
, and Chen
, K. N.
, 2013
, “Low Temperature (<180 °C) Bonding for 3D Integration
,” IEEE International 3D System Integration Conference
(3DIC
), San Francisco, CA, Oct. 2–4, pp. 2
–4
.44.
Korzhavyi
, P. A.
, Abrikosov
, I. A.
, and Johansson
, B.
, 1999
, “First-Principles Calculations of the Vacancy Formation Energy in Transition and Noble Metals
,” Phys. Rev. B
, 59
(18
), p. 11693
.45.
Machlin
, E. S.
, 2010
, An Introduction to Aspects of Thermodynamics and Kinetics Relevant to Materials Science
, Giro Press
, Croton-on-Hudson, NY
, p. 251
.46.
Panigrahi
, A. K.
, Bonam
, S.
, Ghosh
, T.
, Singh
, S. G.
, and Vanjari
, S. R. K.
, 2016
, “Ultra-Thin Ti Passivation Mediated Breakthrough in High Quality Cu–Cu Bonding at Low Temperature and Pressure
,” Mater. Lett.
, 169
, pp. 269
–272
.47.
Panigrahi
, A. K.
, Bonam
, S.
, Ghosh
, T.
, Vanjari
, S. R. K.
, and Singh
, S. G.
, 2015
, “Low Temperature, Low Pressure CMOS Compatible Cu–Cu Thermo-Compression Bonding With Ti Passivation for 3D IC Integration
,” IEEE 65th Electronic Components and Technology Conference
(ECTC
), San Diego, CA, May 26–29, pp. 2205
–2210
.48.
Huang
, Y. P.
, Chien
, Y. S.
, Tzeng
, R. N.
, and Chen
, K. N.
, 2015
, “Demonstration and Electrical Performance of Cu–Cu Bonding at 150 °C with Pd Passivation
,” IEEE Trans. Electron. Devices
, 62
(8
), pp. 2587
–2592
.49.
Huang
, Y.-P.
, Chien
, Y.-S.
, Tzeng
, R.-N.
, and Chen
, K.-N.
, 2015
, “Low Temperature Bonding of Cu/Pd–Pd/Cu Interconnects for Three-Dimensional Integration Applications
,” IEEE International Interconnect Technology Conference (IITC)
, Grenoble, France, May 18–21.50.
Panigrahi
, A. K.
, Ghosh
, T.
, Vanjari
, S. R. K.
, and Singh
, S. G.
, 2017
, “Oxidation Resistive, CMOS Compatible Copper Based Alloy Ultrathin Films as a Superior Passivation Mechanism for Achieving 150 °C Cu–Cu Wafer on Wafer Thermocompression Bonding
,” IEEE Trans. Electron. Dev.
, 64
(3
), pp. 1239
–1245
.51.
Agrawal
, P. M.
, Rice
, B. M.
, and Thompson
, D. L.
, 2002
, “Predicting Trends in Rate Parameters for Self-Diffusion on FCC Metal Surfaces
,” Surf. Sci.
, 515
(1
), pp. 21
–35
.52.
Panigrahi
, A. K.
, Ghosh
, T.
, Vanjari
, S. R. K.
, and Singh
, S. G.
, 2017
, “Demonstration of Sub 150 °C Cu–Cu Thermocompression Bonding for 3D IC Applications, Utilizing an Ultra-Thin Layer of Manganin Alloy as an Effective Surface Passivation Layer
,” Mater. Lett.
, 194
, pp. 86
–89
.53.
Liu
, C. M.
, Lin
, H. W.
, Huang
, Y. S.
, Chu
, Y. C.
, Chen
, C.
, Lyu
, D. R.
, Chen
, K. N.
, and Tu
, K. N.
, 2015
, “Low-Temperature Direct Copper-to-Copper Bonding Enabled by Creep on (111) Surfaces of Nanotwinned Cu
,” Sci. Rep.
, 5
, p. 9734.54.
Lannon
, J. M.
, Jr., Gregory
, C.
, Lueck
, M.
, Huffman
, A.
, Temple
, D.
, Moll
, A. J.
, and Knowlton
, W. B.
, 2010
, “Recent Advances in High Density Area Array Interconnect Bonding for 3D Integration
,” Proc. SPIE
, 7663
, p. 766305
.55.
Suga
, T.
, Itoh
, T.
, Zhonghua
, X.
, Tomita
, M.
, and Yamauchi
, A.
, 2002
, “Surface Activated Bonding for New Flip Chip and Bumpless Interconnect Systems
,” 52nd IEEE Electronic Components and Technology Conference
(ECTC
), San Diego, CA, May 28–31, pp. 105
–111
.56.
Wang
, Y. H.
, and Suga
, T.
, 2008
, “20-μm-Pitch Au Micro-Bump Interconnection at Room Temperature in Ambient Air
,” 58th IEEE Electronic Components and Technology Conference
(ECTC
), Lake Buena Vista, FL, May 27–30, pp. 944
–949
.57.
Elenius
, P.
, and Levine
, L.
, 2000
, “Comparing Flip-Chip and Wire-Bond Interconnection Technologies
,” Chip Scale Rev.
, 4
, p. 81
.58.
Panigrahi
, A. K.
, Kumar
, C. H.
, Ghosh
, T.
, Vanjari
, S. R. K.
, and Singh
, S. G.
, 2017
, “Optimized Ultra-Thin Manganin Alloy Passivated Fine-Pitch Damascene Compatible Cu–Cu Bonding at Sub 200 °C for 3D IC Integration
,” IEEE 5th International Workshop on Low Temperature Bonding for 3D Integration
(LTB-3D
), Tokyo, Japan, May 16–18, p.35.59.
Yang
, Y.-T.
, Chou
, T.-C.
, Yu
, T.-Y.
, Chang
, Y.-W.
, Huang
, T.-Y.
, Yang
, K.-M.
, Ko
, C.-T.
, Chen
, Y.-H.
, Tseng
, T.-J.
, and Chen
, K.-N.
, 2017
, “Low Temperature Cu–Cu Direct Bonding Using Pillar-Concave Structure in Advanced 3D Heterogeneous Integration
,” IEEE Trans. Compon., Packag. Manuf. Technol.
, 7
(9
), pp. 1560
–1566
.60.
Ko
, C.-T.
, Yang
, K.-M.
, Lin
, J.-W.
, Wang
, C.-L.
, Chou
, T.-C.
, Yang
, Y.-T.
, Yu
, T.-Y.
, Chen
, Y.-H.
, Chen
, K.-N.
, and Tseng
, T.-J.
, 2017
, “Study on Low Temperature Cu Bonding and Temporary Bond/De-Bond for RDL-First Fan-out Panel Level Package
,” IEEE 5th International Workshop on Low Temperature Bonding for 3D Integration
(LTB-3D
), Tokyo, Japan, May 16–18.61.
Qin
, Y.
, Howlader
, M. M. R.
, and Deen
, M. J.
, 2015
, “Low-Temperature Bonding for Silicon-Based Micro-Optical Systems
,” Photonics
, 2
(4
), pp. 1164
–1201
.62.
Chipworks, 2016, “
Samsung Galaxy S7 Edge Teardown
,” Chipworks, Ottawa, ON, Canada, accessed Nov. 15, 2017, http://www.chipworks.com/about-chipworks/overview/blog/samsung-galaxy-s7-edge-teardown63.
Tezzaron, 2014, “
2.5/3D Integrated Circuit Technology
,” Tezzaron Semiconductor, Naperville, IL, accessed Nov. 15, 2017, https://tezzaron.com/media/Tezzaron-Presentation-Pixel-090414-for-posting.pdf64.
AZONANO, 2015, “
Tezzaron and Novati Introduce Eight-Layer 3D IC Wafer Stack Containing Active Logic
,” AZoNetwork UK Ltd., Manchester, UK, accessed Nov. 15, 2017, https://www.azonano.com/news.aspx?newsID=3358865.
Tezzaron, 2017, “
DiRAM4™ 3D Memory
,” Tezzaron Semiconductor, Naperville, IL, accessed Nov. 15, 2017, https://tezzaron.com/products/diram4-3d-memory/Copyright © 2018 by ASME
You do not currently have access to this content.
